Implementing Snoop-Coherence Protocol for Future SMP Architectures

Maintaining the coherence is becoming one of the most serious problems faced when designing nowadays machines. Initially, this problem was relatively simple when the interconnection network of Symmetric MultiProcessors (SMP) reduced to an atomic bus which simplified the implementation of invalidation coherence protocols. However, atomic busses have been progressively replaced by split busses that uncoupled the request and response phases of a transaction due to the increasing bandwidth demand. Such busses enable initiating new requests before receiving the response to those already in progress but make more complicate the preservation of the coherence. Indeed, a new request induces a conflict when it concerns a block address involved by another current request and when one of the request is a WRITE miss. Several solutions exist to solve this problem. That one used in the SGI machine is based on a shared data bus which traces the completion of transactions. Unfortunately, it becomes impracticable in the recent machines which replace data busses by more efficient networks (again for bandwidth constrains), ultimately by a crossbar. This work describes and quantitatively evaluates two possible solutions to the coherence problem for the new architectures where each processor cannot trace all the data responses. .